Light erasable memory and method therefor

US7820491B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Rajesh A. Rao · Austin, US
• Leo Mathew · Austin, US
• Ramachandran Muralidhar · Austin, US
• Bruce E. White · Round Rock, US

Key dates

• Filing date: Jan 5, 2007
• Grant date: Oct 26, 2010
• Expiry date: Dec 14, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B20/20

Abstract

A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.