Strained layers within semiconductor buffer structures

US7825401B2 · kind B2 · utility

Assignees

• ASM America, Inc. · US
• S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES · FR

Inventors

• Nyles Wynn Cody · Tempe, US
• Christophe Figuet · Crolles, FR
• Mark Kennard · Crolles, FR

Key dates

• Filing date: Sep 17, 2009
• Grant date: Nov 2, 2010
• Expiry date: Sep 17, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/02532
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same. The at least one strained transitional layer reduces an amount of workpiece bow due to differential coefficient of thermal expansion (CTE) contraction of the relaxed buffer layer relative to CTE contraction of the substrate.