Reduced mask configuration for power MOSFETs with electrostatic discharge (ESD) circuit protection

US7825431B2 · kind B2 · utility

Assignee

• Alpha & Omega Semicondictor, Ltd. · BM

Inventors

• Anup Bhalla · Santa Clara, US
• Xiaobin Wang · Chanhassen, US
• Wei-Chuan Wang · Hamburg, DE
• Yi Su · Sunnyvale, US
• Daniel Ng · Campbell, US

Key dates

• Filing date: Dec 31, 2007
• Grant date: Nov 2, 2010
• Expiry date: Aug 5, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/112

Abstract

A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.