Method and system for grouping logic in an integrated circuit design to minimize number of transistors and number of unique geometry patterns
US7827516B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2008 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Feb 23, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors, and to reduce the total number of unique geometry patterns needed to create the integrated circuit implementation. By grouping the logic functions in terms of a larger number of literals (logic variable inputs), the functions can be implemented in terms of a number of transistors that is often less and no more than equal to that which is required for implementing the same function with a number of logic primitives, or simpler standard logic cells. The optimized transistor level designs are further optimized and physically constructed to reduce the total number of unique geometry patterns required to implement the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.