Patent · US Active

Integrated circuit having ultralow-K dielectric layer

US7829422B2 · kind B2 · utility

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0References

24Claims

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Assignee

Chartered Semiconductor Manufacturing LTD · SG

Inventors

Johnny Widodo · Singapore, SG
Huang Liu · Singapore, SG
Sin Leng Lim · Singapore, SG

Key dates

Filing date	Dec 22, 2006
Grant date	Nov 9, 2010
Priority date	—
Expiry date	Dec 9, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/76834
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A device layer is configured to reduce change in stress characteristics due to subsequent processing to reduce cracking of a subsequently formed layer. The change in stress characteristics can be reduced by providing a shield layer over the device layer to protect the device layer from exposure to subsequently processing, such as curing medium used to form voids in an ultralow-k dielectric layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.