Planarization method using hybrid oxide and polysilicon CMP
US7829464B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 20, 2006 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Feb 3, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.