Patent · US Active

Stackable semiconductor package including laminate interposer

US7829990B1 · kind B1 · utility

15Cited by
241References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 18, 2007
Grant dateNov 9, 2010
Priority date—
Expiry dateMay 29, 2028

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/181
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

An interconnect structure (i.e., a laminate interposer) which is mounted to a semiconductor package leadframe or substrate prior to molding the package body of the semiconductor package. During the molding process, the top of the laminate interposer is protected such that the top surface of the interposer is exposed subsequent to the completion of the molding process. In this manner, electrical signals can be routed from the package leadframe or substrate to the top surface of the package body of the semiconductor package. Subsequently, a mating package can be mounted on top of the underlying package by way of a ball grid array (BGA) interconnect or other type of interconnect.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.