Scheduling threads in a multi-processor computer
US7831980B2 · kind B2 · utility
3Cited by
8References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2008 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Mar 25, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Scheduling threads in a multi-processor computer system including establishing an interrupt threshold for a thread, where the interrupt threshold represents a maximum permissible number of interrupts during thread execution on a processor; executing the thread on a current processor, where the thread has thread affinity for one or more processors including the current processor; counting a number of interrupts during execution of the thread on the current processor; and removing thread affinity for the current processor in dependence upon the counted number of interrupts and the interrupt threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.