Wafer level chip scale package and method of laser marking the same
US7842543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2009 |
| Grant date | Nov 30, 2010 |
| Priority date | — |
| Expiry date | May 3, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer level chip scale package and method of laser marking the same are disclosed. The method includes forming a plurality of semiconductor devices on a frontside surface of a wafer, metallizing device contacts on the frontside surface of the wafer, grinding the backside surface of the wafer, silicon etching the backside surface of the wafer, laser marking the backside surface of the wafer following the silicon etch step, oxide etching the backside surface of the wafer following the laser marking step, depositing a metal layer on the backside surface of the wafer following the oxide etch step, and dicing the wafer into wafer level chip scale packages. A wafer level chip scale package includes a mark formed on a backside surface thereof, the mark comprising a plurality of trenches formed in a silicon backside surface and corresponding indentations formed in an overlaying back metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.