Channel strain engineering in field-effect-transistor
US7842592B2 · kind B2 · utility
1Cited by
1References
19Claims
0Family size
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Key dates
| Filing date | Jun 8, 2007 |
| Grant date | Nov 30, 2010 |
| Priority date | — |
| Expiry date | Oct 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is disclosed a method of applying stress to a channel region underneath a gate of a field-effect-transistor, which includes the gate, a source region, and a drain region. The method includes steps of embedding stressors in the source and drain regions of the FET; forming a stress liner covering the gate and the source and drain regions; removing a portion of the stress liner, the portion of the stress liner being located on top of the gate of the FET; removing at least a substantial portion of the gate of a first gate material and thus creating an opening therein; and filling the opening with a second gate material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.