Method and computer system for optimizing the signal time behavior of an electronic circuit design

US7844931B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Guenther Hutzl · Sindelfingen, DE
• Stephan Held · Bonn, DE
• Juergen Koehl · Holzgerlingen, DE
• Bernhard Korte · Bonn, DE
• Jens Massberg · Bonn, DE
• Matthias Ringe · Lörrach, DE
• Jens Vygen · Bonn, DE

Key dates

• Filing date: Feb 18, 2008
• Grant date: Nov 30, 2010
• Expiry date: Mar 1, 2029

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method and program for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.