Non-volatile memory cell with buried select gate, and method of making same

US7851846B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Nhan Do · Saratoga, US
• Hieu Van Tran · San Jose, US
• Amitay Levi · Cupertino, US

Key dates

• Filing date: Dec 3, 2008
• Grant date: Dec 14, 2010
• Expiry date: Jun 10, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6894

Abstract

A memory device, and method of making the same, in which a trench is formed into the surface of a semiconductor substrate. Source and drain regions define a channel region there between. The drain is formed under the trench. The channel region includes a first portion that extends along a bottom wall of the trench, a second portion that extends along a sidewall of the trench, and a third portion that extends along the surface of the substrate. The floating gate is disposed over the channel region third portion. The control gate is disposed over the floating gate. The select gate is at least partially disposed in the trench and adjacent to the channel region first and second portions. The erase gate disposed adjacent to and insulated from the floating gate.