Patent · US Active

Memory operation testing

US7852692B2 · kind B2 · utility

10Cited by

6References

20Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Shayan Zhang · Cedar Park, US
Jack M. Higman · Austin, US
Michael D. Snyder · Cedar Park, US

Key dates

Filing date	Jun 30, 2008
Grant date	Dec 14, 2010
Priority date	—
Expiry date	Oct 31, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/50012
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Test circuitry for determining whether a memory can operate at a lower operating voltage. The test circuitry includes a sense circuit having a delayed sensing characteristic as compared to other sense amplifier circuits of the memory. With this circuitry, the test circuitry can determine if the sense circuit can provide valid data under more severe sensing conditions. In one example, the sense circuit includes a delay circuit in the sense enable signal path. If sense circuit can provide data at more server operating conditions, then the memory operating voltage can be lowered.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.