Process for design of semiconductor circuits
US7861195B2 · kind B2 · utility
8Cited by
1References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 30, 2008 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | Jan 1, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.