Integrated circuit packaging system with layered packaging and method of manufacture thereof
US7863100B2 · kind B2 · utility
1Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2009 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Mar 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: forming a base package having a base interposer; forming an intermediate package having an intermediate interposer and an intermediate package embedded link trace, the intermediate package embedded link trace being encapsulated in an intermediate package mold compound; forming a cap package having a cap interposer; and connecting the intermediate package to the cap package and the base package using the intermediate package embedded link trace.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.