Methods of forming field effect transistors having silicided source/drain contacts with low contact resistance
US7863201B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 12, 2009 |
| Grant date | Jan 4, 2011 |
| Priority date | — |
| Expiry date | Mar 25, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.