Methods for fabricating dual bit flash memory devices

US7867848B2 · kind B2 · utility

Assignee

• Spansion LLC. · US

Inventors

• Minghao Shen · Road Town, VG
• Fred Cheung · San Jose, US
• Ning Cheung · San Jose, US
• Wei Zheng · Beijing, CN
• Hiroyuki Kinoshita · San Jose, US
• Chih-Yuh Yang · San Jose, US

Key dates

• Filing date: Apr 22, 2010
• Grant date: Jan 11, 2011
• Expiry date: Apr 22, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037

Abstract

Methods for fabricating dual bit memory devices are provided. In an exemplary embodiment of the invention, a method for fabricating a dual bit memory device comprises forming a charge trapping layer overlying a substrate and etching an isolation opening through the charge trapping layer. An oxide layer is formed overlying the charge trapping layer and within the isolation opening. A control gate is fabricated overlying the isolation opening and portions of the charge trapping layer adjacent to the isolation opening. The oxide layer and the charge trapping layer are etched using the control gate as an etch mask and impurity dopants are implanted into the substrate using the control gate as an implantation mask.