FinFET with longitudinal stress in a channel
US7872303B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2008 |
| Grant date | Jan 18, 2011 |
| Priority date | — |
| Expiry date | Dec 23, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/797
Abstract
At least one gate dielectric, a gate electrode, and a gate cap dielectric are formed over at least one channel region of at least one semiconductor fin. A gate spacer is formed on the sidewalls of the gate electrode, exposing end portions of the fin on both sides of the gate electrode. The exposed portions of the semiconductor fin are vertically and laterally etched, thereby reducing the height and width of the at least one semiconductor fin in the end portions. Exposed portions of the insulator layer may also be recessed. A lattice-mismatched semiconductor material is grown on the remaining end portions of the at least one semiconductor fin by selective epitaxy with epitaxial registry with the at least one semiconductor fin. The lattice-mismatched material applies longitudinal stress along the channel of the finFET formed on the at least one semiconductor fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.