Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners
US7875502B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2010 |
| Grant date | Jan 25, 2011 |
| Priority date | — |
| Expiry date | May 27, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01057
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip fabrication method. A provided structure includes: a transistor on a semiconductor substrate, N interconnect layers on the semiconductor substrate and the transistor (N>0), and a first dielectric layer on the N interconnect layers. The transistor is electrically coupled to the N interconnect layers. P crack stop regions and Q crack stop regions are formed on the first dielectric layer (P, Q>0). The first dielectric layer is sandwiched between the N interconnect layers and a second dielectric layer that is formed on the first dielectric layer. Each P crack stop region is completely surrounded by the first and second dielectric layers. The second dielectric layer is sandwiched between the first dielectric layer and an underfill layer that is formed on the second dielectric layer. Each Q crack stop region is completely surrounded by the first dielectric layer and the underfill layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.