Method for fabricating a compound-material wafer
US7892861B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2006 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Aug 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides improved methods for fabricating compound-material wafers, in particular a silicon on insulator type wafer. The improved methods lead to reduced numbers of deflects arising on or near the periphery of the wafers. In a first method, wafers are selected in dependence on edge roll off values determined at about 0.5-2.5 mm away from the edge of the wafer, where edge roll off values are determined in dependence on the second derivative of the wafer height profiles. In a second method, wafers selected according to the first method are further processed by bonding, forming a splitting layer, and detaching the two wafers at the splitting layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.