Inventor · Saint-Martin-d'Hères, FR

Patrick Reynaud

19Patents
5h-index
38Co-inventors
62Inventor score

Filing activity: Jan 16, 2004 → Jan 11, 2018

Most-cited inventions

PatentTitleAreaCited byStatus
US7396357B2 Ancillary tool and method for positioning a prosthetic acetabulum of a hip prosthesis Human Necessities 86 Expired
US7405136B2 Methods for manufacturing compound-material wafers and for recycling used donor substrates Electricity 15 Active
US8821503B2 Ancillary tool and method for positioning a prosthetic acetabulum of a hip prosthesis Human Necessities 8 Active
US7413964B2 Method of revealing crystalline defects in a bulk substrate Physics 8 Active
US7736994B2 Method for manufacturing compound material wafers and corresponding compound material wafer Emerging Cross-Sectional Technologies 8 Active
US8962450B2 Method for manufacturing a semiconductor-on-insulator structure having low electrical losses Electricity 3 Active
US7892861B2 Method for fabricating a compound-material wafer Electricity 2 Active
US7718534B2 Planarization of a heteroepitaxial layer Performing Operations; Transporting 2 Active
US8658514B2 Method for manufacturing a semiconductor-on-insulator structure having low electrical losses, and corresponding structure Electricity 1 Active
US8962492B2 Method to thin a silicon-on-insulator substrate Electricity 1 Active
US8389412B2 Finishing method for a silicon on insulator substrate Electricity 1 Active
US10204786B2 Device for connecting at least one nano-object and method of manufacturing it Electricity 0 Active
US10107772B2 Electronical device for measuring at least one electrical characteristic of an object Physics 0 Active
US9244019B2 Method for measuring defects in a silicon substrate by applying a heat treatment which consolidates and enlarges the defects Physics 0 Active
US9698063B2 Method of testing a semiconductor-on-insulator structure and application of said test to the fabrication of such a structure Electricity 0 Active
US9293473B2 Method for manufacturing a semiconductor on insulator structure having low electrical losses Electricity 0 Active
US10858244B2 Device for connecting at least one nano-object associated with a chip enabling a connection to at least one external electrical system and method of fabrication thereof Electricity 0 Active
US11373856B2 Support for a semiconductor structure Electricity 0 Active
US9653536B2 Method for fabricating a structure Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.