Integrated circuit system employing sacrificial spacers
US7892900B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2008 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Jun 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0184
Abstract
An integrated circuit system that includes: providing a substrate including a first device and a second device; configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made from a sacrificial spacer material; forming a second dielectric layer over the integrated circuit system; forming a first device source/drain and a second device source/drain adjacent the second spacer and through the second dielectric layer; removing the second spacer without damaging the substrate; forming a third dielectric layer over the integrated circuit system before annealing; and forming a fourth dielectric layer over the integrated circuit system that promotes stress within the channel of the first device, the second device, or a combination thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.