Cache sharing based thread control
US7895415B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2007 |
| Grant date | Feb 22, 2011 |
| Priority date | — |
| Expiry date | Dec 24, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and computing systems associated with cache sharing based thread control are described. One embodiment includes a memory to store a thread control instruction and a processor to execute the thread control instruction. The processor is coupled to the memory. The processor includes a first unit to dynamically determine a cache sharing behavior between threads in a multi-threaded computing system and a second unit to dynamically control the composition of a set of threads in the multi-threaded computing system. The composition of the set of threads is based, at least in part, on thread affinity as exhibited by cache-sharing behavior. The thread control instruction controls the operation of the first unit and the second unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.