Method for creating tensile strain by selectively applying stress memorization techniques to NMOS transistors

US7897451B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Maciej Wiatr · Dresden, DE
• Casey Scott · Dresden, DE
• Andreas Gehring · Dresden, DE
• Peter Javorka · Radebeul, DE
• Andy Wei · Queensbury, US

Key dates

• Filing date: May 20, 2008
• Grant date: Mar 1, 2011
• Expiry date: May 20, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

By selectively applying a stress memorization technique to N-channel transistors, a significant improvement of transistor performance may be achieved. High selectivity in applying the stress memorization approach may be accomplished by substantially maintaining the crystalline state of the P-channel transistors while annealing the N-channel transistors in the presence of an appropriate material layer which may not to be patterned prior to the anneal process, thereby avoiding additional lithography and masking steps.