Dielectric-sandwiched pillar memory device
US7897954B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2008 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Mar 23, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes bottom and top electrode structures and a memory cell therebetween. The memory cell comprises bottom and top memory elements and a dielectric element therebetween. A lower resistance conduction path is formed through the dielectric element. The dielectric element may have an outer edge and a central portion, the outer edge being thicker than the central portion. To make a memory device, an electrical pulse is applied through the memory cell to form a conduction path through the dielectric element. A passivation element may be formed by oxidizing the outer surface of the memory cell which may also enlarge the outer edge of the dielectric element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.