Patent · US Active

Semiconductor constructions having multiple patterned masking layers over NAND gate stacks

US7898019B2 · kind B2 · utility

2Cited by

5References

4Claims

0Family size

Assignee

Micron Technology, Inc. · US

Inventors

David J. Keller · Syracuse, US
Hongbin Zhu · Boise, US
Alex J. Schrinsky · Boise, US

Key dates

Filing date	Dec 9, 2008
Grant date	Mar 1, 2011
Priority date	—
Expiry date	Apr 7, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH10B41/35
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern through a carbon-containing layer. The patterned carbon-containing layer may be used to pattern NAND cell unit gates. Some embodiments include structures having a patterned carbon-containing layer defining a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.