Patent · US Active

Block contact architectures for nanoscale channel transistors

US7898041B2 · kind B2 · utility

101Cited by
282References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 14, 2007
Grant dateMar 1, 2011
Priority date
Expiry dateFeb 1, 2028

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/017

Abstract

A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.