Method and apparatus for creating a gate optimization evaluation library
US7899637B2 · kind B2 · utility
9Cited by
7References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2007 |
| Grant date | Mar 1, 2011 |
| Priority date | — |
| Expiry date | Nov 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.