Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection
US7902604B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2009 |
| Grant date | Mar 8, 2011 |
| Priority date | — |
| Expiry date | Mar 16, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/126
Abstract
A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.