Methods for forming small-scale capacitor structures

US7906393B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Lingyi A. Zheng · Boise, US
• Trung T. Doan · Los Gatos, US
• Lyle Breiner · Meridian, US
• Er-Xuan Ping · Boise, US
• Kevin L. Beaman · Boise, US
• Ronald A. Weimer · Boise, US
• Cem Basceri · Boise, US
• David J. Kubista · Nampa, US

Key dates

• Filing date: Jan 28, 2004
• Grant date: Mar 15, 2011
• Expiry date: Aug 8, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/712
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 Å.