High compressive stress carbon liners for MOS devices

US7906817B1 · kind B1 · utility

Assignee

• Novellus Systems, Inc. · US

Inventors

• Qingguo Wu · Vancouver, US
• James S. Sims · Tigard, US
• Mandyam Sriram · Beaverton, US
• Seshasayee Varadarajan · Lake Oswego, US
• Haiying Fu · West Linn, US
• Pramod Subramonium · Beaverton, US
• Jon Henri · West Linn, US
• Sirish Reddy · Hillsboro, US

Key dates

• Filing date: Jun 6, 2008
• Grant date: Mar 15, 2011
• Expiry date: Jul 9, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0212
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide amorphous carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.