Integrated scheme for forming inter-poly dielectrics for non-volatile memory devices

US7910446B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Yi Ma · Orlando, US
• Shreyas Kher · Campbell, US
• Khaled Ahmed · Anaheim, US

Key dates

• Filing date: Jun 27, 2008
• Grant date: Mar 22, 2011
• Expiry date: Jun 8, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

Electronic devices and methods for forming electronic devices that allow for a reduction in device dimensions while also maintaining or reducing leakage current for non-volatile memory devices are provided. In one embodiment, a method of fabricating a non-volatile memory device is provided. The method comprises depositing a floating gate polysilicon layer on a substrate, forming a silicon oxide layer on the floating gate polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a high-k dielectric material layer on the first silicon oxynitride layer, depositing a second silicon oxynitride on the high-k dielectric material, and forming a control gate polysilicon layer on the second silicon oxynitride layer. In one embodiment, the high-k dielectric material layer comprises hafnium silicon oxynitride.