Gapfill improvement with low etch rate dielectric liners
US7910491B2 · kind B2 · utility
86Cited by
16References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 2009 |
| Grant date | Mar 22, 2011 |
| Priority date | — |
| Expiry date | Jul 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02274
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of filling a trench is described and includes depositing a dielectric liner with a high ratio of silicon oxide to dielectric liner etch rate in fluorine-containing etch chemistries. Silicon oxide is deposited within the trench and etched to reopen or widen a gap near the top of the trench. The dielectric liner protects the underlying substrate during the etch process so the gap can be made wider. Silicon oxide is deposited within the trench again to substantially fill the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.