Wafer level I/O test, repair and/or customization enabled by I/O layer
US7913202B2 · kind B2 · utility
16Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2007 |
| Grant date | Mar 22, 2011 |
| Priority date | — |
| Expiry date | Jul 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design structure for a 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.