Method and system for variable thread allocation and switching in a multithreaded processor
US7917907B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2005 |
| Grant date | Mar 29, 2011 |
| Priority date | — |
| Expiry date | Sep 19, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor. The method further switches the processing from a first one of the active threads to a next one of the active threads upon the occurrence of the variable thread switch timeout state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.