Edge seal for thru-silicon-via technology
US7919834B2 · kind B2 · utility
3Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2007 |
| Grant date | Apr 5, 2011 |
| Priority date | — |
| Expiry date | Jan 12, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/04941
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One or more multilayer back side metallurgy (BSM) stack structures are formed on thru-silicon-vias (TSV). The multiple layers of metal may include an adhesion layer of chromium on the semiconductor wafer back side, a conductive layer of copper, diffusion barrier layer of nickel and a layer of nobel metal, such as, gold. To prevent edge attack of copper after dicing, the layer of nickel is formed to seal the copper edge. To also prevent edge attack of the layer of nickel after dicing, the layer of gold is formed to seal both the layer of copper and the layer of nickel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.