Patent · US Active

Wafer level surface passivation of stackable integrated circuit chips

US7923349B2 · kind B2 · utility

31Cited by

32References

25Claims

0Family size

Assignee

Vertical Circuits, Inc. · US

Inventors

Simon J. S. McElrea · Scotts Valley, US
Terrence Caskey · Santa Cruz, US
Scott McGrath · Scotts Valley, US
DeAnn Eileen Melcher · San Jose, US
Reynaldo Co · Scotts Valley, US
Lawrence Douglas Andrews, JR. · Soquel, US
Weiping Pan · San Jose, US
Grant Villavicencio · Scotts Valley, US
Yong Du · Timonium, US
Scott Jay Crane · Aromas, US
Zongrong Liu · Pleasanton, US

Key dates

Filing date	Jun 19, 2008
Grant date	Apr 12, 2011
Priority date	—
Expiry date	Nov 1, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/1461
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.