Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon

US7923365B2 · kind B2 · utility

Assignees

• SAMSUNG ELECTRONICS CO., LTD. · KR
• International Business Machines Corporation · US
• Chartered Semiconductor Manufacturing LTD · SG
• Infineon Technologies AG · DE

Inventors

• Jun Jung Kim · Seojong-myeon, KR
• Sang-Jine Park · Seojong-myeon, KR
• Min Ho Lee · Siheung-si, KR
• Thomas W. Dyer · Pleasant Valley, US
• Sunfei Fang · Lagrangeville, US
• O-Sung Kwon · Wappingers Falls, US
• Johnny Widodo · Singapore, SG

Key dates

• Filing date: Oct 17, 2007
• Grant date: Apr 12, 2011
• Expiry date: Feb 20, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0212

Abstract

Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.