Method for training dynamic random access memory (DRAM) controller timing delays
US7924637B2 · kind B2 · utility
22Cited by
16References
23Claims
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Key dates
| Filing date | Mar 31, 2008 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Feb 27, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller (114, 116) are trained. A left edge of passing receive enable delay values is determined (530). A final value of a receive data strobe delay value and a final value of a transmit data delay value are trained (540). A right edge of passing receive enable delay values is determined using a working value of the receive data strobe delay (550); and a final receive enable delay value intermediate between the left edge of passing receive enable delay values and the right edge of passing receive enable delay values is set (560).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.