Transistor devices with nano-crystal gate structures
US7928502B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2010 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Mar 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Embodiments of non-volatile semiconductor devices include a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric, and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.