Segmentation of a die stack for 3D packaging thermal management
US7928562B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2008 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Mar 12, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16251
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.