Stress optimization in dual embedded epitaxially grown semiconductor processing
US7935593B2 · kind B2 · utility
5Cited by
2References
27Claims
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Key dates
| Filing date | Feb 5, 2009 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Jul 4, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide stress optimization during manufacturing of dual embedded epitaxially grown (EPI) semiconductor structures using just two masks, such as nFET and pFET open for embedded epitaxial using SiC and SiGe, and separated halo implantation masks for both horizontal and vertical PC
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.