Wafer level chip packaging

US7936062B2 · kind B2 · utility

Assignee

• Tessera Technologies Ireland Limited · IE

Inventors

• Giles Humpston · San Jose, US
• Michael J. Nystrom · San Jose, US
• Vage Oganesian · Sunnyvale, US
• Yulia Aksenton · Jerusalem, IL
• Osher Avsian · Huntersville, US
• Robert Burtzlaff · San Jose, US
• Avi Dayan · Jerusalem, IL
• Andrey Grinman · Jerusalem, IL
• Felix Hazanovich · Nes Ziona, IL
• Ilya Hecht · Bet Shemesh, IL
• Charles Rosenstein · Bet Shemesh, IL
• David Ovrutsky · San Jose, US
• Mitchell Hayes Reifel · Irvine, US

Key dates

• Filing date: Jan 19, 2007
• Grant date: May 3, 2011
• Expiry date: May 2, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3025
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Packaged microelectronic elements are provided. In an exemplary embodiment, a microelectronic element having a front face and a plurality of peripheral edges bounding the front face has a device region at the front face and a contact region with a plurality of exposed contacts adjacent to at least one of the peripheral edges. The packaged element may include a plurality of support walls overlying the front face of the microelectronic element such that a lid can be mounted to the support walls above the microelectronic element. For example, the lid may have an inner surface confronting the front face. In a particular embodiment, some of the contacts can be exposed beyond edges of the lid.