Process for fabricating a substrate of the silicon-on-insulator type with reduced roughness and uniform thickness

US7939427B2 · kind B2 · utility

Assignee

• S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES · FR

Inventors

• Eric Neyret · Saint-Égrève, FR
• Francois Boedt · Meylan, FR

Key dates

• Filing date: Sep 4, 2007
• Grant date: May 10, 2011
• Expiry date: May 5, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76254
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process for fabricating a silicon on insulator (SOI) substrate by co-implanting atomic or ionic species into a semiconductor donor substrate to form a weakened zone therein, the weakened zone forming a boundary between a thin silicon active layer and the remainder of the donor substrate. The donor substrate is then bonded to a semiconductor receiver substrate by molecular adhesion, resulting in a layer of buried silicon interposed between the donor substrate and the receiver substrate. The remainder of the donor substrate is detached along the weakened zone to obtain a SOI substrate with the receiver substrate covered with the buried oxide layer and the thin silicon active layer. The silicon active layer is then thermally annealed for at least 10 minutes in a gaseous atmosphere containing hydrogen, argon or both at a temperature of at least 950° C. but not exceeding 1100° C. The annealing step minimizes roughness of the surface of the silicon active layer, prevents reduction in thickness of the buried oxide layer, and achieves uniform thickness of the thin silicon active layer and the buried oxide layer.