High density via and metal interconnect structures, and methods of forming the same
US7939445B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2008 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Jun 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76838
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and structures for interconnects in semiconductor devices are described. A method of forming a mask pattern for a metal layer in an interconnect can include searching a layout for a metal feature with a predetermined size and an interconnect layer aligned thereto, removing the metal feature from the layout to form a modified layout, and reforming the mask pattern using the modified layout. The metal interconnect may include a first pattern of metal lines, each having a minimum feature size in a layout view in no more than one dimension; a dielectric layer on or over the first pattern of metal lines, having a substantially planar horizontal upper surface; and vias or contacts in the dielectric layer, the vias or contacts contacting a top surface of the first pattern of metal lines and a top surface of silicon structures, vias, or contacts below the first pattern of metal lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.