Nano-tube MOSFET technology and devices
US7943989B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2008 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Dec 31, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/112
Abstract
This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.