Method and apparatus for delaying a load miss flush until issuing the dependent instruction
US7953960B2 · kind B2 · utility
1Cited by
8References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2005 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Jan 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipeline processor has circuits to detect the presence of a register access instruction in an issue stage of the pipeline. A load-miss occurring at a later stage may cause the register access instruction to be marked with an associated bit. The register access instruction progresses down the pipeline and when the flush stage is reached, the processor checks the associated bit and flushes the register access instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.