Method of producing an asymmetric architecture semi-conductor device

US7955914B2 · kind B2 · utility

Assignees

• STMicroelectronics SA
• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

• Serdar Manakli · Grenoble, FR
• Jessy Bustos · Le Touvet, FR
• Philippe Coronel · Barraux, FR
• Laurent Pain · Voiron, FR

Key dates

• Filing date: Oct 2, 2008
• Grant date: Jun 7, 2011
• Expiry date: Jul 21, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6757
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method is for producing an asymmetric architecture semiconductor device. The device includes a substrate, and in stacked relation, a first photosensitive layer, a non-photosensitive layer, and a second photosensitive layer. The method includes a first step of exposing a first zone in each of the photosensitive layers by a first beam of electrons traversing the non-photosensitive layer. A second step includes exposing at least one second zone of one of the two photosensitive layers by a second beam of electrons or photons or ions, thereby producing a widening of one of the first zones compared to the other first zone such that the second zone is in part superimposed on one of the first zones.