Patent · US Active

Method for manufacturing semiconductor device comprising SOI transistors and bulk transistors

US7955937B2 · kind B2 · utility

5Cited by

10References

7Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Karsten Wieczorek · Dresden, DE
Manfred Horstmann · Dresden, DE
Thomas Feudel · Radebeul, DE
Thomas J. Heller, Jr. · Seneca, US

Key dates

Filing date	Nov 17, 2006
Grant date	Jun 7, 2011
Priority date	—
Expiry date	Oct 10, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH10D87/00
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

By forming bulk-like transistors in sensitive RAM areas of otherwise SOI-based CMOS circuits, a significant savings in valuable chip area may be achieved since the RAM areas may be formed on the basis of a bulk transistor configuration, thereby eliminating hysteresis effects that may typically be taken into consideration by providing transistors of increased transistor width or by providing body ties. Hence, the benefit of high switching speed may be maintained in speed-critical circuitry, such as CPU cores, while at the same time the RAM circuit may be formed in a highly space-efficient manner.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.