Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods
US7960229B2 · kind B2 · utility
8Cited by
1References
10Claims
0Family size
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Key dates
| Filing date | Apr 10, 2008 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Jun 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6713
Abstract
A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.